Static Verification - using Hardware Property Language (HPL)

PCI Express Device Verification.

Static Verification has been carried out on all layers of the     PCI Express Bridge device.         Transaction Layer         Data Link Layer         Physical Layer (Digital section)         Power Management Status and Control         Configuration Register Space

Property Specification Language (PSL)

Create Verification IP using PSL

Full Functional Simulation Models for Memories and Peripherals

Bus Functional Models

Test bench/Test case development

Vector Generation

Test Matrix Creation

Bus-Watchers

Random Cycle Generators

Cycle Collision Detectors

Assembly Language Coding