The Synchronous Serial Bus Core is compatible with any I2C
device operating upto 100 Kbits/Sec in Normal Mode and 400 Kbits/Sec in Fast Mode
operation. It comprises of 2 lines the SCLK (Clock Signal) and SDA (Data Signal). The
device can operate as a Transmitter, Receiver or both and can be initialized with a unique
address. Transfers can only be initiated in Master mode only. The master provides the
clock signal that controls the transfer.This core is available in Verilog (please email info@ishnatek.com for documentation on
implimentation & testbench ).