| Products | |
 | |
| Design Services | |
| |
| Verification | |
| |
| Library Services | |
| |
| Consultancy Services | |
| |
| Request Form | |
| |
| News | |
| |
| Contact Us | |
 |
 ASIC Design
Services |
| RTL Design - Verilog and
VHDL |
| Intellectual Property (IP)
Development |
| Integration of
Cores |
| Synthesis |
| Design
for Power - Low Power Design Techniques |
| Re-Target Designs to Newer
technologies |
| Verilog-to-VHDL & VHDL-to-Verilog Code
Conversions |
| Gatelevel Netlist to High-Level Designs
[Verilog/VHDL] |
| Design For Testability
(DFT) |
 info@ishnatek.com with questions or comments about this web site.Copyright © 2004 Ishna Tek Systems And Services Private Limited. Last modified: 07/23/2004 |